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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Down
Figure 71: READ to Power-Down Entry
BL = 4
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK#
CK
CKE 1, 2
RL
t ISCK E
CMD
DQ
DQS#
DQS
BL = 8
READ
D OUT D OUT D OUT D OUT
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK#
CK
RL
t ISCK E
CKE
1, 2
CMD
DQ
DQS#
DQS
READ
D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at (RL + RU( t DQSCK(MAX)/ t CK) + BL/2 + 1) clock cycles after
the clock on which the READ command is registered.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
96
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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